Why RAM timings include both tRAS and tRC
This isn’t the most important part of memory tuning, but it’s a fun mystery to work through.
tRAS and tRC are restrictions on when you can issue activate (opening a row) and precharge (closing a row) commands to a bank of memory. You can’t precharge unless it’s been at least tRAS cycles since activation, and you can’t activate unless it’s been at least tRC cycles since the last activation. tRP is the other relevant timing here: it’s how long is needed for a precharge to do its thing. The effective tRC is always at least tRAS+tRP, since there’s no way to activate again anyway until both tRAS and tRP cycles have elapsed.
The long-standing mystery here is why we have both tRAS and tRC. Either can seemingly do the other’s job just fine, and they do just that on pre-AM5 platforms. Intel platforms don’t even have tRC, it’s just implied to be tRAS+tRP and this works fine. AM4 has both, but in practice tRC is the one that matters and tRAS can be set to the motherboard’s minimum with no ill effects.
AM5’s new behavior is that very low tRAS settings (30 is my motherboard’s minimum) only work with very high tRC settings (up around 150 in my testing). 36-34-34-30-150 is stable, 36-34-36-62-98 is possibly stable (note the tRP of 36), and 36-34-34-66-100 is stable. I haven’t nailed down the exact slopes.
If there’s a tradeoff like this, at first glance you’d much rather minimize the gap between tRAS and tRC. After all, we’re only precharging so that we can activate something else, and tRC delays that activate if tRAS+tRP doesn’t. 36-34-34-60-100 is potentially faster than 36-34-34-66-100 though because of contention. What if the memory controller has something better to be doing than issuing a precharge when 66 rolls around? If it doesn’t get around to the precharge until 76, then it drives the effective tRC up to 110. 36-34-34-60-100 gives it some slack; precharges no longer have to be issued at the perfect time to maintain 100 cycles between activations. There’s probably not a performance reason to have a very large gap, though.
On the stability side, we can look at tRC as boosting the effective tRP when precharges happen shortly after activates. In the extreme case of 36-34-34-30-150, tRP effectively needs to be 120 to stabilize a precharge issued 30 cycles after an activate.
There’s one more subtle stability gotcha hiding in this mess. Say for example that your RAM requires tRP 30 at tRAS 70, tRP 35 at tRAS 60, and tRP 40 at tRAS 50. You set tRP to 30, tRAS to 50, and tRC to 90. Things seem stable at first. Doing any real work takes longer than tRAS and long enough that the base tRP of 30 is fine, and if it’s trying to precharge immediately after an activate then the tRC of 90 extends the effective tRP enough for stability. What happens though if the memory controller is busy and doesn’t get around to issuing the precharge until 60 cycles after the activate? Effective tRP needs to be 35, but tRC is only 90, so the memory controller thinks it’s good to go 5 cycles too early. Oops!
As far as I can tell, the best all-around tuning process is to minimize tRP, then minimize tRC while decreasing tRAS in lockstep to maintain tRAS + tRP = tRC, then minimize tRAS. This avoids the possibility of any subtle unstable corners that might appear at lower tRC while still getting most of the possible performance advantages.
tRTP and tWR are also likely to have some specific optimal places around this part of the process, but I’m not sure what they would be.